Semiconductor memories, such as dynamic random access memories (DRAM), typically employ small, regular cell units (e.g. 4 Mb) which are combined to form larger configurations, such as 64 Mb, 128, and 256 Mb configurations, for example. Additionally, DRAM memories often employ a folded bitline architecture and a cell structure commonly referred to as an 8F2-type cell, which consists of one bitline pair and one wordline, resulting in a cell area of 8F2, where F is the minimum feature size. Such cell characteristics, together with the page size of DRAMs which, according to industry standards (e.g. JEDEC), comprise a binary number of bits (e.g. 2 k), dictate the form factor of a DRAM die employing such conventional architecture.
In many applications, it is desirable for a DRAM die to have a roughly square form factor (i.e. approximately a 1:1 aspect ratio). For example, the “ball-outs” of some standardized packages lend themselves to a square die for minimum package size (e.g. the 60 ball JEDEC package for low power DRAM), and according to the Known-Good-Die business, square DRAM dies, which fit best to a square ASIC or microprocessor die in a multi-chip package, are preferred.
DRAMs of the above-described conventional architecture having densities of 32 Mb, 128 Mb, and 512 Mb, for example, typically have a substantially square form factor (i.e. 1:1 aspect ratio). However, DRAMs having densities of 16 Mb, 64 Mb, 256 Mb, and 1 Gb, for example, typically have an aspect ratio of approximately 2:1. While a 2:1 aspect ratio can be quite easily modified to attain a 4:1 aspect ratio, a 1:1 aspect ratio is not readily achievable as the cell array would need to be delineated at a non-binary number, which conflicts with the standardized binary page size. In other cases, neither the square architecture nor a 4:1 aspect ratio (e.g. a 512 Mb array) will fit well with a given package configuration.
One technique currently employed to achieve an approximately square form factor for certain memory densities, such as 256 Mb and 1 Gb, is to partition the array into eight parts, each of which has a square form factor (e.g. 256 Mb/8=32 Mb, having a 1:1 aspect ratio). These eight parts are then arranged to form the outside blocks of a 3×3 field of blocks (e.g. a ring-like shape), with the center of the 3×3 field of blocks being used for peripheral and logic circuitry. While a roughly square form factor is achieved using this technique, chip area is wasted as the peripheral and logic circuitry does not require the full area of the center block of the field, and difficult timing conditions are created as internal data and control signal flow is different for different memory blocks.
Another technique is to employ a 6F2-type cell. However, such cell types are not compatible with all DRAM capacitor types and require major technological development for manufacturers currently using 8F2-type cells.